実験室メール送れないぢゃん。 library IEEE; use IEEE.std_logic_1164.all; entity core is port ( CLK : in std_logic; SEN : in std_logic; CLR : in std_logic; LOD : out std_logic; WRI : out std_logic; RES : out std_logic; COU : out std_logic ); end core; architecture RTL of core is signal load,resi,write,switch,count : std_logic; begin process(CLK,CLR) begin if (CLR = '0') then load <= '0'; write <= '0'; resi <= '0'; switch <= '0'; count <= '0'; elsif(CLK'event and CLK = '1') then count <= '1'; if(load = '0' and SEN = '0' and write = '0') then load <= '1'; switch <= '1'; write <= write; resi <= resi; elsif(load = '1' and switch = '1' and write = '0') then load <= '0'; write <= '1'; switch <= switch; resi <= resi; elsif(load = '0' and switch = '1' and write = '1') then write <= '0'; resi <= '1'; load <= load; switch <= switch; elsif(SEN = '1' and resi = '1' and switch = '1') then resi <= '0'; switch <= '0'; load <= load; write <= write; else load <= load; write <= write; resi <= resi; switch <= switch; end if; end if; end process; LOD <= load; WRI <= write; RES <= resi; COU <= count after 1ns; end RTL;
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